Generally, a plurality of LED-related areas is formed on a wafer in a wafer-forming process. Each of the LED-related areas is provided with two electrodes for example. Conventionally, the wafer is subjected to a cutting process so that the LED-related areas are separated from one another and become individual LED chips. Each of the LED chips includes an upper side on which the electrodes are formed and a periphery. Each of the LED chips is subjected to a packaging process so that it is sealed with a protective film except the electrodes. That is, the periphery and the upper side except the electrodes are covered with the protective film. For use, the electrodes of the LED are connected to a printed circuit board for example.
As disclosed in U.S. Pat. No. 6,946,683, a wafer is divided into a plurality of LED chips in a cutting process. Each of the LED chips is formed with an epitaxial layer 11, a conductive layer 13, an isolating layer 4, a first terminal 3, a semiconductor 2 and a second terminal 6. Then, an upper side of the semiconductor 2 is covered with a protective film, and a periphery of the semiconductor 2 is covered with another protective film. The provision of the protective films is conducted in a packaging process after the cutting process. Although not addressed, a periphery of the conductive layer 13 must be covered with another protective film in another packaging process before each of the LED chips can be used. Obviously, it requires a wafer-forming process, a cutting process and at least one packaging process before an LED chip can be used, and this is complicated and expensive.
According to U.S. Patent Publication No. 2004/0121562 A1, FIG. 5, a substrate 10 includes semiconductor elements formed thereon. Internal wiring 24 is formed across a boundary between adjacent semiconductor elements. An oxide film is formed between the substrate 10 and the internal wiring 24. The internal wiring 24 is connected to the semiconductor elements via contact holes (S10). The semiconductor substrate 10 is sandwiched between an upper carrier 2 and a lower carrier 3. Resin layers 5 are located between the substrate 10 and the upper carrier 2, while other resin layers 5 are located between the substrate 10 and the carrier 3, thus forming a laminated structure 100 (S12). At this step, the substrate 10 is etched from the lower carrier 3 along a scribe line to temporarily expose the internal wiring 24 before laminating the lower carrier 3 onto the substrate 10. Buffer members 30 are formed on the lower carrier 3. The buffer members 30 serve as cushions for relieving stress applied to the ball-shaped terminals 8. Then, a notch 22 is created in the laminated structure 100 from the lower carrier 3 along the scribe line using a dicing saw 34, as shown in FIG. 6, to expose end portions 26 of the internal wiring 24 of the elements to a side of the notch 22 (S14). A metal film 28 is formed on the lower carrier member 3 and the internal surface of the notch 22 (S16) so that the metal film 28 contacts the internal wiring 24. The metal film 28 is patterned according to a predetermined wiring pattern to form external wiring lines 7 that extend from the internal wiring 24 to the buffer members 30 (S18). A protection film 32 and ball-shaped terminals 8 are formed (S19, S20). Finally, the laminated structure 100 is divided along the scribe line to produce individual semiconductor devices packaged in a chip size package (S22). The spirit is providing a coolant during the use of the saw. However, end portions of the external wiring 7 are not covered with any protective film. A protective film must be provided to cover the end portions of the external wiring 7 after the cutting, and this is complicated and expensive.
Therefore, the present invention has arisen to mitigate and/or obviate the afore-described disadvantages of the conventional methods.